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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(kicad_pcb (version 20171130) (host pcbnew 5.1.9)
First commit
2019-03-03 14:23:10 +00:00
(general
(thickness 1.6)
(drawings 29)
(tracks 561)
(zones 0)
(modules 52)
(nets 134)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
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(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
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(uvia_size 0.3)
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(uvias_allowed no)
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(uvia_min_drill 0.1)
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(edge_width 0.1)
(segment_width 0.2)
First commit
2019-03-03 14:23:10 +00:00
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(net 0 "")
(net 1 /uController/SDA)
(net 2 /uController/SCL)
(net 3 /uController/vin_arduino)
(net 4 GND)
(net 5 +3V3)
(net 6 +5V)
(net 7 /uController/MOSI)
(net 8 /uController/SCK)
(net 9 +12V)
(net 10 /Power/3G)
(net 11 /Power/3F)
(net 12 /Power/3E)
(net 13 /Power/3D)
(net 14 /Power/3C)
(net 15 /Power/3B)
(net 16 /Power/3A)
(net 17 /Power/2A)
(net 18 /Power/2B)
(net 19 /Power/2C)
(net 20 /Power/2D)
(net 21 /Power/2E)
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(net 23 /Power/2G)
(net 24 /Power/DOTS)
(net 25 /Power/1G)
(net 26 /Power/1F)
(net 27 /Power/1E)
(net 28 /Power/1D)
(net 29 /Power/1C)
(net 30 /Power/1B)
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(net 32 /Power/~A~)
(net 33 /Power/~B~)
(net 34 /Power/~C~)
(net 35 /Power/~D~)
(net 36 /Power/A)
(net 37 /Power/B)
(net 38 /Power/C)
(net 39 /Power/D)
(net 40 /Power/horn)
(net 41 /Power/green2)
(net 42 /Power/orange2)
(net 43 /Power/red2)
(net 44 /Power/green)
(net 45 /Power/orange)
(net 46 /Power/red)
(net 47 /uController/AD17)
(net 48 /uController/AD16)
(net 49 /uController/AD15)
(net 50 /uController/AD14)
(net 51 /uController/AD10)
(net 52 /Power/A7)
(net 53 /Power/A6)
(net 54 /uController/AD11)
(net 55 /uController/AD12)
(net 56 /uController/AD13)
(net 57 /Power/A5)
(net 58 /Power/A4)
(net 59 /Power/A3)
(net 60 /Power/A0)
(net 61 /Power/A1)
(net 62 /Power/A2)
(net 63 /Power/E0)
(net 64 /Power/E1)
(net 65 /Power/E2)
(net 66 /Power/E3)
(net 67 /Power/E4)
(net 68 /Power/E5)
(net 69 /Power/E6)
(net 70 /Power/E7)
(net 71 /Power/D7)
(net 72 /Power/D6)
(net 73 /Power/D5)
(net 74 /Power/D4)
(net 75 /Power/D3)
(net 76 /Power/D2)
(net 77 /Power/D1)
(net 78 /Power/D0)
(net 79 /Power/C0)
(net 80 /Power/C1)
(net 81 /Power/C2)
(net 82 /Power/C3)
(net 83 /Power/C4)
(net 84 /Power/C5)
(net 85 /Power/C6)
(net 86 /Power/C7)
(net 87 /Power/jolly0)
(net 88 /Power/jolly1)
(net 89 /Power/jolly2)
(net 90 "Net-(SHIELD1-Pad14)")
(net 91 "Net-(SHIELD1-Pad15)")
(net 92 "Net-(SHIELD1-Pad16)")
(net 93 "Net-(SHIELD1-Pad17)")
(net 94 "Net-(SHIELD1-PadRST)")
(net 95 "Net-(SHIELD1-Pad0)")
(net 96 "Net-(SHIELD1-Pad1)")
(net 97 "Net-(SHIELD1-Pad38)")
(net 98 "Net-(SHIELD1-Pad39)")
(net 99 /uController/MISO)
(net 100 /uController/~CE~)
(net 101 /uController/IRQ)
(net 102 /uController/~CSN~)
(net 103 /uController/xbee_out)
(net 104 /uController/xbee_in)
(net 105 "Net-(J9-Pad4)")
(net 106 "Net-(J9-Pad5)")
(net 107 "Net-(J9-Pad6)")
(net 108 "Net-(J9-Pad7)")
(net 109 "Net-(J9-Pad8)")
(net 110 "Net-(J9-Pad9)")
(net 111 /Power/horn_p)
(net 112 /Power/green_p)
(net 113 /Power/orange_p)
(net 114 /Power/red_p)
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(net 116 "Net-(Q4-Pad1)")
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(net 118 /uController/mute)
(net 119 /uController/lr)
(net 120 /uController/DIG2)
(net 121 /uController/DIG3)
(net 122 /DIG4)
(net 123 /DIG5)
(net 124 /DIG6)
(net 125 /DIG7)
(net 126 /uController/DIG11)
(net 127 /uController/DIG12)
(net 128 /uController/DIG13)
(net 129 "Net-(Q3-Pad1)")
(net 130 "Net-(J9-Pad3)")
(net 131 /uController/+12_in)
(net 132 "Net-(JP2-Pad2)")
(net 133 /uController/bright)
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(add_net /DIG4)
(add_net /DIG5)
(add_net /DIG6)
(add_net /DIG7)
(add_net /Power/A0)
(add_net /Power/A1)
(add_net /Power/A2)
(add_net /Power/A3)
(add_net /Power/A4)
(add_net /Power/A5)
(add_net /Power/A6)
(add_net /Power/A7)
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(add_net /Power/C1)
(add_net /Power/C2)
(add_net /Power/C3)
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(add_net /Power/D1)
(add_net /Power/D2)
(add_net /Power/D3)
(add_net /Power/D4)
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(add_net /Power/E4)
(add_net /Power/E5)
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(add_net /uController/AD10)
(add_net /uController/AD11)
(add_net /uController/AD12)
(add_net /uController/AD13)
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(add_net /uController/AD15)
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(add_net /uController/AD17)
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(add_net /uController/DIG3)
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(add_net /uController/MOSI)
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(add_net "Net-(Q4-Pad1)")
(add_net "Net-(SHIELD1-Pad0)")
(add_net "Net-(SHIELD1-Pad1)")
(add_net "Net-(SHIELD1-Pad14)")
(add_net "Net-(SHIELD1-Pad15)")
(add_net "Net-(SHIELD1-Pad16)")
(add_net "Net-(SHIELD1-Pad17)")
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(net_class LightSupply ""
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(add_net +3V3)
(add_net +5V)
(add_net /uController/+12_in)
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(net_class Power ""
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(add_net +12V)
(add_net /Power/1A)
(add_net /Power/1B)
(add_net /Power/1C)
(add_net /Power/1D)
(add_net /Power/1E)
(add_net /Power/1F)
(add_net /Power/1G)
(add_net /Power/2A)
(add_net /Power/2B)
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(add_net /Power/2E)
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(add_net /Power/3C)
(add_net /Power/3D)
(add_net /Power/3E)
(add_net /Power/3F)
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(add_net /Power/B)
(add_net /Power/C)
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(add_net /Power/green)
(add_net /Power/green2)
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(add_net /Power/horn_p)
(add_net /Power/jolly0)
(add_net /Power/jolly1)
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(add_net /Power/orange)
(add_net /Power/orange2)
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(add_net /Power/red)
(add_net /Power/red2)
(add_net /Power/red_p)
(add_net /Power/~A~)
(add_net /Power/~B~)
(add_net /Power/~C~)
(add_net /Power/~D~)
(add_net /uController/vin_arduino)
(add_net GND)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Horizontal (layer B.Cu) (tedit 59FED5CB) (tstamp 5C4AFB61)
(at 5.5245 81.534 180)
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(fp_line (start 2.135 1.27) (end 4.04 1.27) (layer B.Fab) (width 0.1))
rev2.0
2021-02-16 16:57:42 +00:00
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First commit
2019-03-03 14:23:10 +00:00
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(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
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2021-02-16 16:57:42 +00:00
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First commit
2019-03-03 14:23:10 +00:00
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(module Capacitor_THT:CP_Radial_D4.0mm_P1.50mm (layer F.Cu) (tedit 5AE50EF0) (tstamp 5C48E90D)
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(tags "CP Radial series Radial pin pitch 1.50mm diameter 4mm Electrolytic Capacitor")
(path /5C77064C/5C7826E9)
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
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rev2.0
2021-02-16 16:57:42 +00:00
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
)
rev2.0
2021-02-16 16:57:42 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.2 1.2) (drill 0.6) (layers *.Cu *.Mask)
(net 3 /uController/vin_arduino))
(pad 2 thru_hole circle (at 1.5 0) (size 1.2 1.2) (drill 0.6) (layers *.Cu *.Mask)
(net 4 GND))
(model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Radial_D4.0mm_P1.50mm.wrl
First commit
2019-03-03 14:23:10 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
rev2.0
2021-02-16 16:57:42 +00:00
(module Connector_Phoenix_MSTB:PhoenixContact_MSTBVA_2,5_4-G_1x04_P5.00mm_Vertical (layer F.Cu) (tedit 5B785046) (tstamp 5C48E7C0)
(at 24.765 11.43)
(descr "Generic Phoenix Contact connector footprint for: MSTBVA_2,5/4-G; number of pins: 04; pin pitch: 5.00mm; Vertical || order number: 1755532 12A || order number: 1924211 16A (HC)")
(tags "phoenix_contact connector MSTBVA_01x04_G_5.00mm")
(path /5C73A3FE/5C2F1A6F)
(fp_text reference J7 (at -4.953 3.7465) (layer F.SilkS)
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(effects (font (size 1 1) (thickness 0.15)))
First commit
2019-03-03 14:23:10 +00:00
)
rev2.0
2021-02-16 16:57:42 +00:00
(fp_text value Screw_Terminal_01x04 (at 7.5 5) (layer F.Fab)
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.61 -4.91) (end -3.61 3.91) (layer F.SilkS) (width 0.12))
rev2.0
2021-02-16 16:57:42 +00:00
(fp_line (start -3.61 3.91) (end 18.61 3.91) (layer F.SilkS) (width 0.12))
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(fp_line (start 18.61 -4.91) (end -3.61 -4.91) (layer F.SilkS) (width 0.12))
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(fp_line (start -3.5 -4.8) (end -3.5 3.8) (layer F.Fab) (width 0.1))
rev2.0
2021-02-16 16:57:42 +00:00
(fp_line (start -3.5 3.8) (end 18.5 3.8) (layer F.Fab) (width 0.1))
(fp_line (start 18.5 3.8) (end 18.5 -4.8) (layer F.Fab) (width 0.1))
(fp_line (start 18.5 -4.8) (end -3.5 -4.8) (layer F.Fab) (width 0.1))
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(fp_line (start -3.61 -4.1) (end -1.11 -4.1) (layer F.SilkS) (width 0.12))
rev2.0
2021-02-16 16:57:42 +00:00
(fp_line (start 18.61 -4.1) (end 16.11 -4.1) (layer F.SilkS) (width 0.12))
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(fp_line (start 1 -4.1) (end 4 -4.1) (layer F.SilkS) (width 0.12))
rev2.0
2021-02-16 16:57:42 +00:00
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
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rev2.0
2021-02-16 16:57:42 +00:00
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(fp_line (start 16 -3.1) (end 14 -3.1) (layer F.SilkS) (width 0.12))
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
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rev2.0
2021-02-16 16:57:42 +00:00
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
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rev2.0
2021-02-16 16:57:42 +00:00
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(fp_line (start 17.7 2.2) (end 17 2.2) (layer F.SilkS) (width 0.12))
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(fp_line (start -4 -5.3) (end -4 4.3) (layer F.CrtYd) (width 0.05))
rev2.0
2021-02-16 16:57:42 +00:00
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
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rev2.0
2021-02-16 16:57:42 +00:00
(fp_arc (start 0 0.55) (end -2 2.2) (angle -100.5) (layer F.SilkS) (width 0.12))
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(fp_arc (start 10 0.55) (end 8 2.2) (angle -100.5) (layer F.SilkS) (width 0.12))
(fp_arc (start 15 0.55) (end 13 2.2) (angle -100.5) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 7.5 -4.1) (layer F.Fab)
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
rev2.0
2021-02-16 16:57:42 +00:00
(pad 1 thru_hole roundrect (at 0 0) (size 2 3.6) (drill 1.4) (layers *.Cu *.Mask) (roundrect_rratio 0.125)
(net 111 /Power/horn_p))
(pad 2 thru_hole oval (at 5 0) (size 2 3.6) (drill 1.4) (layers *.Cu *.Mask)
(net 114 /Power/red_p))
(pad 3 thru_hole oval (at 10 0) (size 2 3.6) (drill 1.4) (layers *.Cu *.Mask)
(net 113 /Power/orange_p))
(pad 4 thru_hole oval (at 15 0) (size 2 3.6) (drill 1.4) (layers *.Cu *.Mask)
(net 112 /Power/green_p))
(model ${KISYS3DMOD}/Connector_Phoenix_MSTB.3dshapes/PhoenixContact_MSTBVA_2,5_4-G_1x04_P5.00mm_Vertical.wrl
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
rev2.0
2021-02-16 16:57:42 +00:00
(module Connector_Phoenix_MSTB:PhoenixContact_MSTBVA_2,5_2-G_1x02_P5.00mm_Vertical (layer F.Cu) (tedit 5B785046) (tstamp 5C2E2591)
(at 4.826 94.996 180)
(descr "Generic Phoenix Contact connector footprint for: MSTBVA_2,5/2-G; number of pins: 02; pin pitch: 5.00mm; Vertical || order number: 1755516 12A || order number: 1924198 16A (HC)")
(tags "phoenix_contact connector MSTBVA_01x02_G_5.00mm")
(path /5C77064C/5C78270E)
(fp_text reference BT1 (at 7.8105 4.8895 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
)
rev2.0
2021-02-16 16:57:42 +00:00
(fp_text value 12/24V (at 2.5 5 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
First commit
2019-03-03 14:23:10 +00:00
)
rev2.0
2021-02-16 16:57:42 +00:00
(fp_line (start -0.5 -3.55) (end 0.5 -3.55) (layer F.Fab) (width 0.1))
(fp_line (start 0 -2.55) (end -0.5 -3.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.5 -3.55) (end 0 -2.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.3 -5.71) (end 0.3 -5.71) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -5.11) (end -0.3 -5.71) (layer F.SilkS) (width 0.12))
(fp_line (start 0.3 -5.71) (end 0 -5.11) (layer F.SilkS) (width 0.12))
(fp_line (start 9 -5.3) (end -4 -5.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 9 4.3) (end 9 -5.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -4 4.3) (end 9 4.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -4 -5.3) (end -4 4.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 7.7 2.2) (end 7 2.2) (layer F.SilkS) (width 0.12))
(fp_line (start 7.7 -3.1) (end 7.7 2.2) (layer F.SilkS) (width 0.12))
(fp_line (start -2.7 -3.1) (end 7.7 -3.1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.7 2.2) (end -2.7 -3.1) (layer F.SilkS) (width 0.12))
(fp_line (start -2 2.2) (end -2.7 2.2) (layer F.SilkS) (width 0.12))
(fp_line (start 2 2.2) (end 3 2.2) (layer F.SilkS) (width 0.12))
(fp_line (start 6 -3.1) (end 4 -3.1) (layer F.SilkS) (width 0.12))
(fp_line (start 6 -4.91) (end 6 -3.1) (layer F.SilkS) (width 0.12))
(fp_line (start 4 -4.91) (end 6 -4.91) (layer F.SilkS) (width 0.12))
(fp_line (start 4 -3.1) (end 4 -4.91) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -3.1) (end -1 -3.1) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -4.91) (end 1 -3.1) (layer F.SilkS) (width 0.12))
(fp_line (start -1 -4.91) (end 1 -4.91) (layer F.SilkS) (width 0.12))
(fp_line (start -1 -3.1) (end -1 -4.91) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -4.1) (end 4 -4.1) (layer F.SilkS) (width 0.12))
(fp_line (start 8.61 -4.1) (end 6.11 -4.1) (layer F.SilkS) (width 0.12))
(fp_line (start -3.61 -4.1) (end -1.11 -4.1) (layer F.SilkS) (width 0.12))
(fp_line (start 8.5 -4.8) (end -3.5 -4.8) (layer F.Fab) (width 0.1))
(fp_line (start 8.5 3.8) (end 8.5 -4.8) (layer F.Fab) (width 0.1))
(fp_line (start -3.5 3.8) (end 8.5 3.8) (layer F.Fab) (width 0.1))
(fp_line (start -3.5 -4.8) (end -3.5 3.8) (layer F.Fab) (width 0.1))
(fp_line (start 8.61 -4.91) (end -3.61 -4.91) (layer F.SilkS) (width 0.12))
(fp_line (start 8.61 3.91) (end 8.61 -4.91) (layer F.SilkS) (width 0.12))
(fp_line (start -3.61 3.91) (end 8.61 3.91) (layer F.SilkS) (width 0.12))
(fp_line (start -3.61 -4.91) (end -3.61 3.91) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 2.5 -4.1 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 5 0.55) (end 3 2.2) (angle -100.5) (layer F.SilkS) (width 0.12))
(fp_arc (start 0 0.55) (end -2 2.2) (angle -100.5) (layer F.SilkS) (width 0.12))
(pad 2 thru_hole oval (at 5 0 180) (size 2 3.6) (drill 1.4) (layers *.Cu *.Mask)
(net 4 GND))
(pad 1 thru_hole roundrect (at 0 0 180) (size 2 3.6) (drill 1.4) (layers *.Cu *.Mask) (roundrect_rratio 0.125)
(net 9 +12V))
(model ${KISYS3DMOD}/Connector_Phoenix_MSTB.3dshapes/PhoenixContact_MSTBVA_2,5_2-G_1x02_P5.00mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Jumper:SolderJumper-3_P1.3mm_Open_Pad1.0x1.5mm (layer B.Cu) (tedit 5A3F8BB2) (tstamp 5C455F16)
(at 54.356 60.198)
(descr "SMD Solder 3-pad Jumper, 1x1.5mm Pads, 0.3mm gap, open")
(tags "solder jumper open")
(path /5C77064C/5C391796)
(attr virtual)
(fp_text reference JP2 (at 0 1.8) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Jumper_NC_Dual (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.3 -1.2) (end -1 -1.5) (layer B.SilkS) (width 0.12))
(fp_line (start -1.6 -1.5) (end -1 -1.5) (layer B.SilkS) (width 0.12))
(fp_line (start -1.3 -1.2) (end -1.6 -1.5) (layer B.SilkS) (width 0.12))
(fp_line (start -2.05 -1) (end -2.05 1) (layer B.SilkS) (width 0.12))
(fp_line (start 2.05 -1) (end -2.05 -1) (layer B.SilkS) (width 0.12))
(fp_line (start 2.05 1) (end 2.05 -1) (layer B.SilkS) (width 0.12))
(fp_line (start -2.05 1) (end 2.05 1) (layer B.SilkS) (width 0.12))
(fp_line (start -2.3 1.25) (end 2.3 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1.25) (end -2.3 -1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 -1.25) (end 2.3 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 -1.25) (end -2.3 -1.25) (layer B.CrtYd) (width 0.05))
First commit
2019-03-03 14:23:10 +00:00
(pad 3 smd rect (at 1.3 0) (size 1 1.5) (layers B.Cu B.Mask)
(net 4 GND))
(pad 2 smd rect (at 0 0) (size 1 1.5) (layers B.Cu B.Mask)
(net 132 "Net-(JP2-Pad2)"))
(pad 1 smd rect (at -1.3 0) (size 1 1.5) (layers B.Cu B.Mask)
(net 5 +3V3))
)
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Horizontal (layer B.Cu) (tedit 59FED5CB) (tstamp 5C3D87CB)
(at 5.5245 68.961 180)
(descr "Through hole angled pin header, 1x02, 2.54mm pitch, 6mm pin length, single row")
(tags "Through hole angled pin header THT 1x02 2.54mm single row")
(path /5C77064C/5C384D02)
(fp_text reference SW2 (at 11.2395 -1.143 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value SW_Push (at 4.385 -4.81 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(fp_line (start 10.55 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
rev2.0
2021-02-16 16:57:42 +00:00
(fp_line (start 10.55 -4.35) (end 10.55 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -4.35) (end 10.55 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end -1.8 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.27 1.27) (end 0 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end -1.27 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.92) (end 1.44 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.16) (end 1.44 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.92) (end 4.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.16) (end 10.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -2.16) (end 10.1 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -1.27) (end 4.1 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 -0.38) (end 1.44 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 0.38) (end 1.44 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.28) (end 10.1 -0.28) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.16) (end 10.1 -0.16) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.04) (end 10.1 -0.04) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.08) (end 10.1 0.08) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.2) (end 10.1 0.2) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.32) (end 10.1 0.32) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -0.38) (end 4.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 0.38) (end 10.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.38) (end 10.1 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 1.33) (end 1.44 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -3.87) (end 4.1 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -3.87) (end 4.1 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 1.33) (end 1.44 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start 4.04 -2.86) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -2.22) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -2.22) (end 10.04 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.86) (end 1.5 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end -0.32 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end 1.5 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 0.32) (end 10.04 0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end 1.5 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end -0.32 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end 1.5 0.32) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 0.635) (end 2.135 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 -3.81) (end 1.5 0.635) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -3.81) (end 1.5 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 1.27) (end 4.04 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 2.135 1.27) (end 4.04 1.27) (layer B.Fab) (width 0.1))
First commit
2019-03-03 14:23:10 +00:00
(fp_text user %R (at 2.77 -1.27 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 118 /uController/mute))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Horizontal (layer B.Cu) (tedit 59FED5CB) (tstamp 5C3D73E3)
(at 5.5245 75.2475 180)
(descr "Through hole angled pin header, 1x02, 2.54mm pitch, 6mm pin length, single row")
(tags "Through hole angled pin header THT 1x02 2.54mm single row")
(path /5C77064C/5C384C1A)
(fp_text reference SW1 (at 11.43 -1.3335 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value SW_Push (at 4.385 -4.81 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
(fp_line (start 10.55 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
rev2.0
2021-02-16 16:57:42 +00:00
(fp_line (start 10.55 -4.35) (end 10.55 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -4.35) (end 10.55 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end -1.8 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.27 1.27) (end 0 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end -1.27 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.92) (end 1.44 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.16) (end 1.44 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.92) (end 4.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.16) (end 10.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -2.16) (end 10.1 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -1.27) (end 4.1 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 -0.38) (end 1.44 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 0.38) (end 1.44 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.28) (end 10.1 -0.28) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.16) (end 10.1 -0.16) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.04) (end 10.1 -0.04) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.08) (end 10.1 0.08) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.2) (end 10.1 0.2) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.32) (end 10.1 0.32) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -0.38) (end 4.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 0.38) (end 10.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.38) (end 10.1 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 1.33) (end 1.44 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -3.87) (end 4.1 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -3.87) (end 4.1 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 1.33) (end 1.44 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start 4.04 -2.86) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -2.22) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -2.22) (end 10.04 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.86) (end 1.5 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end -0.32 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end 1.5 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 0.32) (end 10.04 0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end 1.5 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end -0.32 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end 1.5 0.32) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 0.635) (end 2.135 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 -3.81) (end 1.5 0.635) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -3.81) (end 1.5 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 1.27) (end 4.04 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 2.135 1.27) (end 4.04 1.27) (layer B.Fab) (width 0.1))
First commit
2019-03-03 14:23:10 +00:00
(fp_text user %R (at 2.77 -1.27 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 GND))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 119 /uController/lr))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Logos:golem-logo-15mm (layer B.Cu) (tedit 0) (tstamp 5C3BF086)
(at 44.196 64.516 180)
(path /5C34EDA5)
(fp_text reference LOGO2 (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 1.524 1.524) (thickness 0.3)) (justify mirror))
)
(fp_text value GOLEM-logo (at 0.75 0 180) (layer B.SilkS) hide
(effects (font (size 1.524 1.524) (thickness 0.3)) (justify mirror))
)
rev2.0
2021-02-16 16:57:42 +00:00
(fp_poly (pts (xy 1.268042 5.066336) (xy 1.416312 4.968099) (xy 1.430459 4.955018) (xy 1.505336 4.876962)
(xy 1.542661 4.811008) (xy 1.554997 4.730259) (xy 1.55575 4.686777) (xy 1.534496 4.530853)
(xy 1.476897 4.388994) (xy 1.392189 4.279909) (xy 1.334765 4.23928) (xy 1.220018 4.204285)
(xy 1.079013 4.194064) (xy 0.941713 4.20861) (xy 0.852215 4.23939) (xy 0.738282 4.334207)
(xy 0.666533 4.462467) (xy 0.637727 4.609485) (xy 0.652624 4.760577) (xy 0.711982 4.901057)
(xy 0.812211 5.012863) (xy 0.956439 5.089611) (xy 1.111566 5.107138) (xy 1.268042 5.066336)) (layer B.SilkS) (width 0.01))
(fp_poly (pts (xy -0.953485 5.0827) (xy -0.816759 5.002203) (xy -0.715929 4.880031) (xy -0.660954 4.726075)
(xy -0.653891 4.652512) (xy -0.679383 4.503479) (xy -0.754373 4.375918) (xy -0.866417 4.277319)
(xy -1.003072 4.215172) (xy -1.151893 4.196967) (xy -1.300438 4.230193) (xy -1.331244 4.244831)
(xy -1.465313 4.345618) (xy -1.547272 4.481276) (xy -1.577826 4.625198) (xy -1.563158 4.788032)
(xy -1.495527 4.927259) (xy -1.383864 5.033471) (xy -1.237099 5.097257) (xy -1.116149 5.111632)
(xy -0.953485 5.0827)) (layer B.SilkS) (width 0.01))
(fp_poly (pts (xy -1.027739 -1.139909) (xy -0.971898 -1.174818) (xy -0.9525 -1.205819) (xy -0.975239 -1.235192)
(xy -1.031563 -1.228863) (xy -1.097195 -1.19322) (xy -1.135628 -1.150799) (xy -1.135147 -1.124563)
(xy -1.091798 -1.118868) (xy -1.027739 -1.139909)) (layer B.SilkS) (width 0.01))
(fp_poly (pts (xy -0.94728 -1.340531) (xy -0.902798 -1.374526) (xy -0.864033 -1.422552) (xy -0.83517 -1.473525)
(xy -0.845524 -1.490994) (xy -0.862903 -1.49225) (xy -0.924042 -1.471359) (xy -0.94615 -1.45415)
(xy -0.97775 -1.403056) (xy -0.981141 -1.356698) (xy -0.956089 -1.338578) (xy -0.94728 -1.340531)) (layer B.SilkS) (width 0.01))
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First commit
2019-03-03 14:23:10 +00:00
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(module Logos:oshw-logo-15mm (layer B.Cu) (tedit 0) (tstamp 5C3BF068)
(at 31.4325 64.7065 180)
(path /5C34EED5)
(fp_text reference LOGO1 (at 0 0 180) (layer B.SilkS) hide
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(fp_text value Logo_Open_Hardware_Small (at 0.75 0 180) (layer B.SilkS) hide
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[PCB] Power traces thickness
2021-02-16 16:54:42 +00:00
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2021-02-16 16:57:42 +00:00
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